The present invention relates to a method for manufacturing a capacitor of a semiconductor memory device, and more particularly, to a method for manufacturing a capacitor of a semiconductor memory device having high cell capacitance and increased reliability in a dynamic random access memory (DRAM) device constructed by integrating a plurality of cells each of which consists a transmitting transistor and a charge-storage area of the capacitor.
As the integration of a semiconductor memory device is increased, the area occupied by each cell is decreased. Generally, if the cell size is decreased, the effective area of a charge-storage capacitor is decreased, and as a result, its capacitance is also decreased. Such a decrease in the capacitance of DRAM cells increases a soft error rate and lowers the refresh function of the cell. Thus, a method for increasing cell capacitance by enlarging the effective area of the capacitor, to compensate for the decrease of the cell size, has been widely sought. This kind of method for increasing the cell capacitance has been an objective in the high-integration of semiconductor memory devices. Among the methods are a stacked structure in which a capacitor is formed by stacking a plurality of layers on a silicon substrate, and a trench structure in which a capacitor is formed by trenching a semiconductor substrate.
FIG. 1 is a cross-sectional view of the structure of a typical stacked capacitor. Here, a field oxide layer 11 for device isolation, a gate electrode pattern consisting of a gate oxide layer 12, a gate conductive layer 13 and an upper insulating layer 14 are formed on a semiconductor substrate 10. A spacer 15 for forming a self-aligned contact on the side wall of the gate electrode pattern and a first insulating layer 16 for insulating the gate electrode is formed on the gate electrode pattern. A storage electrode 17, a dielectric layer 18 and a plate electrode 19 are formed on first insulating layer 16 and semiconductor substrate 10, to thereby construct a capacitor, and a second insulating layer 20 and a bit-line 21 are formed on plate electrode 19.
In the stacked capacitor (STC) structure discussed above, only the top surface area of the storage electrode is used for the charge-storage of the capacitor. Thus, the STC structure cannot provide a suitable cell capacitance for smaller cells, which has been the ongoing trend according in higher integration of semiconductor memory devices, such as 16 Mb DRAM devices and beyond. To solve this problem, a new single stacked wrap (SSW) structure has been developed.
FIG. 2 is a cross-sectional diagram of the SSW structure, and the same reference numerals of FIG. 2 as those of FIG. 1 represent the same components.
Referring to FIG. 2, differently from the STC structure, dielectric layer 25 and plate electrode 26 are formed by additionally using a part of the lower surface of storage electrode 24 as an effective capacitor area, and a nitride layer 22 and an oxide layer 23 are further formed on the first insulating layer 16.
In this SSW structure, since the upper top and a part of lower surfaces of the storage electrode are used for the charge storage of the capacitor, the cell capacitance is increased compared with that of the STC structure. Here, however, the SSW structure cannot provide a suitable cell capacitance for the smaller cells, such as for 16 Mb DRAM devices and beyond either.
Thus, as shown in FIG. 3, a fin structure capacitor is recommended for securing sufficient cell capacitance.
Referring to FIG. 3, which is a cross-sectional diagram of the fin structure capacitor, storage electrode 28 is constructed as double layers and dielectric layer 29 and plate electrode 30 are formed, to thereby form the capacitor. In this structure, the storage layers can be constructed as multiple layers so that the sufficient effective area of the capacitor can be obtained even though the cell area is small. However, it is difficult to perform the necessary processes. That is, since a polysilicon layer and an oxide layer should be alternately dry-etched during the etching process for forming the storage electrode pattern, much etching equipment is required and processing costs are increased accordingly. Also, due to the multi-layered storage electrode, the topology of the cell is very poor. If the polysilicon layer is not sufficiently over-etched for forming the storage electrode, poly-stringers contaminate the periphery circuitry, to thereby lower the reliability of the memory device.
To improve the above problems, a capacitor having a semi-double fin (SDF) structure has been suggested.
Referring to FIGS. 4A to 4F, the method for manufacturing the capacitor having an SDF structure will be described.
In FIG. 4A, using a device isolating method, a field oxide layer 34 is formed on a semiconductor substrate 32, to define the active regions. Subsequently, after gate insulating layer 36, gate conductive layer 38 and upper insulating layer 40 are stacked, the gate electrode pattern is formed by a photolithography process. Impurity ions are injected into the active region, to form a source region 42 and a drain region 44. Then, spacer 46 is formed on the sidewalls of the gate electrode pattern.
In FIG. 4B, a first insulating layer 48 such as a high-temperature oxide (HTO) layer, a first conductive layer 50 such as a polysilicon layer, and a second insulating layer 52 such as an HTO layer are sequentially stacked on the whole surface of the above resultant structure on which the gate electrode pattern is formed.
In FIG. 4C, a photoresist is deposited on the second insulating layer 52 and the resultant structure is patterned to form a first photoresist pattern 54. Thereafter, second insulating layer 52, first conductive layer 50 and first insulating layer 48 are sequentially etched to expose source region 42, to thereby form a contact hole h.
In FIG. 4D, first photoresist pattern 54 is removed and then second conductive layer 56 is formed on the resultant structure on which contact hole h is formed. Thereafter, the photoresist is deposited on second conductive layer 56 and then second photoresist pattern 58 for forming the storage electrode pattern is formed.
In FIG. 4E, second conductive layer 56 is dry-etched using second photoresist pattern 58 as an etching mask. Then, second insulating layer 52 is wet-etched using a solution such as a buffered oxide etchant (BOE). Then, first conductive layer 50 is dry-etched, to thereby form the storage electrode.
In FIG. 4F, a dielectric layer 58 and a plate electrode 60 and an insulating layer 62 are sequentially etched on the above resultant. Then, a contact hole is formed over drain region 44, and a bit-line 64 is formed.
In contrast to the conventional STC or SSW structure, sufficient cell capacitance is easily secured using the SDF structure. Also, the manufacturing process is simpler than that of the fin-structured capacitor, to thereby provide for excellent reliability.
However, it is difficult for the SDF structure to be applied to a capacitor over bit-line (COB) structure in which the capacitor is formed on the bit-line. In the COB structure, the bit-line is formed prior to capacitor formation, which is in contrast to the conventional structure in which the capacitor is formed before the bit-line. The COB structure will be described with reference to FIGS. 5-7. (Here, too, the same reference numerals represent the same components.)
Referring to FIG. 5, a field oxide 72 for device isolation and a gate electrode pattern consisting of a gate insulating layer 73, a gate electrode 74 and an upper insulating layer 75 are formed on a semiconductor substrate 71. A spacer 78 for forming a self-aligned contact is formed on the sidewalls of the gate electrode pattern, and a polysilicon pad 79 is formed on a source region 76 and a drain region 77. On the other hand, bit-line 80 is formed, to be surrounded by an insulating layer such as a boro-phosphorus silicon glass (BPSG) layer 81, on polysilicon pad 79 formed on drain region 77. Also, polysilicon pad 79 formed on source region 76 is connected to a storage electrode 82 via a contact.
As described above, in the COB structure, the bit-line is formed prior to the capacitor. Since the undercut of storage electrode 82 is planarized by BPSG layer 81, the surface area of storage electrode 82 increases. Also, the photolithography process can be easily performed for the cell structure and a sufficient design margin can be secured.
However, in the COB structure, the BPSG layer is used as the insulating layer instead of an HTO layer, for planarizing the storage electrode. Here, the BPSG layer has a greater wet-etching rate than the HTO layer. Thus, during a cleaning process after the contact hole is formed, the side of the BPSG layer is wet-etched by the cleaning solution such as hydrofluoric acid (HF), to thereby enlarge the contact hole. As a result, a void is generated in storage electrode 82 so that reliability is lowered. Also, since storage electrode 82, which is doped within the contact hole, contacts BPSG layer 81 of the side of the hole, the boron and phosphorus of BPSG layer 81 migrates into storage electrode 82 during a subsequent thermal process, which also decreases reliability.
To overcome the above problems, there is recommended a structure in which spacer 83 made of an insulating substance having a low wet-etching rate, such as Si.sub.3 N.sub.4 or SiON, is formed on the sidewalls of BPSG layer 81 contacting storage electrode 82, as shown in FIG. 6.
However, when the capacitor of the above SDF structure is applied to the COB structure, as shown in FIG. 7, since a first conductive layer 84 and a second conductive layer 86 are separated by a spacer 85 serving as an insulator, there is no contact between first and second conductive layers 84 and 86 within the contact hole.